Designing a Logical Circuit Using Inverting Decoders and NAND Gates

Designing a logical circuit to provide a logical one at the output whenever any two but only two of the three input signals are high is a common problem in digital electronics. This article will guide you through the process using a 3-to-8 inverting decoder, specifically the 74xx183, and a 3-input NAND gate, such as the 74xx10. By following the steps outlined, we will ensure the circuit meets the specified requirements.

Step 1: Truth Table and Boolean Expression

The design begins with a truth table that has three inputs (A, B, C) and one output (Z). Here, the truth table is:

CBAZ 0000 0010 0100 0111 1000 1011 1101 1110

From the truth table, we observe that Z is high only when exactly two inputs are high. The Boolean expression derived from this truth table is:

$$Z AB'C A'BC A'B'C'$$

Using this expression, let's implement the circuit.

Step 2: Circuit Implementation

The first step is to implement the inverting decoder. We will use the 74xx183 IC, which is a 3-to-8 inverting decoder. The outputs of the decoder are /A, /B, /C, /A'B, /A'C, /B'A, /B'C, /A'B'C'. We need to connect the appropriate outputs to a 3-input NAND gate, such as the 74xx10.

Step 3: Wiring Outputs to NAND Gate

Wire the /3, /5, and /6 outputs of the 74xx183 to the 3 inputs of a 3-input NAND gate (74xx10). These outputs correspond to /A'B'C', A'B', and A'C respectively. This setup will ensure that the NAND gate outputs high only when any two of the three inputs are high, and the third input is low.

Step 4: Testing the Circuit

To test the circuit, you can use a logic analyzer or a digital multimeter to verify that the output is high only when any two of the three inputs are high and the third is low. This can be done by systematically setting the inputs to different combinations and observing the output.

Alternative Approach

For a more intuitive approach, you can design the circuit by building three parallel sub-circuits. Here is a detailed breakdown of how to implement it:

Sub-circuit 1:

Take any two signals (A and B) and feed them to an AND gate. The output of this AND gate will be high only when both A and B are high. Feed the third signal (C) through an inverter. If the third signal is high, the inverter output will be low, and the AND gate output will be low. If the third signal is low, the inverter output will be high, and the AND gate output will be high only if A and B are both high.

Sub-circuit 2:

Take the first signal (A) and the third signal (C) and feed them to an AND gate. The output of this AND gate will be high only when both A and C are high. Feed the second signal (B) through an inverter. If the second signal is high, the inverter output will be low, and the AND gate output will be low. If the second signal is low, the inverter output will be high, and the AND gate output will be high only if A and C are both high.

Sub-circuit 3:

Take the second signal (B) and the third signal (C) and feed them to an AND gate. The output of this AND gate will be high only when both B and C are high. Feed the first signal (A) through an inverter. If the first signal is high, the inverter output will be low, and the AND gate output will be low. If the first signal is low, the inverter output will be high, and the AND gate output will be high only if B and C are both high.

The final step is to OR the outputs of the three sub-circuits. If exactly two of the signals are high, one of the sub-circuits will generate a high output, and the OR gate will provide the desired output.

Check out Tom Crosley’s answer to this question for alternative approaches and additional insights.

Conclusion

Designing a logical circuit to provide a logical one at the output whenever any two but only two of the three input signals are high requires careful consideration of the input combinations and the use of appropriate logic gates. By following the steps outlined in this article, you can efficiently implement the circuit using inverting decoders and NAND gates.

Keywords: logical circuit, inverting decoder, NAND gate