The Shortest Instructions in Modern CPUs and Their Execution Time

Modern CPUs can execute some instructions in zero clock cycles, which is indeed impressive. One example is the MOV BX AX instruction in certain scenarios. This instruction doesn't perform any actual computation; it merely updates internal register information. The work is done by the instruction decoder, and no execution time is required. Let's explore what this means and how it fits into the broader context of modern CPU architecture.

Defining Modern CPUs and Their Instructions

When discussing modern CPUs, we are referring to the latest desktop and laptop CPUs. These CPUs have distinct characteristics regarding their instruction set and execution parameters.

Instruction Parameters

Size: The number of bytes the instruction occupies. Execution Time: The number of clock cycles required to execute the instruction.

ARM and x86/x64 Architecture

Two dominant CPU architectures today, ARM and x86/x64, have distinct features. ARM CPU instructions are fixed-width, typically 32 bits (4 bytes), while x86/x64 instructions can vary in length, from 1 to 15 bytes.

The shortest instruction in the x86/x64 world is NOP (No Operation). In the ARM world, all instructions are 4 bytes, thus the shortest instruction is any instruction.

Historical Perspective on Execution Speed

Comparison with older architectures like the 6502 reveals the advancements in modern CPUs. The 6502 CPU executed instructions sequentially, with most instructions taking 2 clock cycles: one for loading and one for execution. This sequential model was then improved with the introduction of pipelined execution, which allowed for the execution of multiple instructions in parallel.

Pipelined Execution

In pipelined execution, the 6502 could combine the loading and execution steps of simple instructions, thus reducing the execution time from 2 cycles to 1 cycle. This parallel processing revolutionized how CPUs managed instruction execution.

Modern Superscalar Architecture

Modern CPUs are based on superscalar architecture, which significantly improves instruction throughput. Here, instructions are first decoded and then transformed into micro-operations (uOps). These uOps can be executed in parallel, depending on the core's complexity. For example, a single instruction might be transformed into multiple uOps, which can then be executed simultaneously.

To illustrate, the NOP instruction, which takes 2 clock cycles on a 6502 and 1 cycle on more modern cores, can be executed in just 0.2 cycles on an Intel Tiger/ Ice Lake architecture. This means that 5 NOP instructions can be executed in a single clock cycle.

Even though the total execution time includes loading, decoding, transforming into uOps, and actual execution stages, the parallel nature of these operations results in an effectively shorter execution time. For example, an addition that would take 3-4 clock cycles on a 6502 CPU might take only 0.2-0.3 clock cycles on a modern core.

Conclusion

The shortest instructions in modern CPUs and their execution times highlight the advancements in CPU architecture and instruction processing. While the concept of zero-cycle instructions might seem surreal, it is a result of sophisticated instruction decoding and parallel execution techniques. Understanding these intricacies is crucial for those working with modern CPUs, whether in software development, system-level programming, or performance tuning.